Navigation¶
Introduction¶
| Page | Description |
|---|---|
| Overview | What this project is, the two models it provides, and how the repository is organized. |
| Installation | Prerequisites and setup steps for building and running the models. |
| Getting Started | A hands-on walkthrough: build both models, run a simple test, view the trace, and run the validation suite. |
Writing and Running Programs¶
| Page | Description |
|---|---|
| Assembly Programs | How to write, assemble, and run your own assembly test programs. |
| C Programs | How to write, compile, and run freestanding C test programs. |
| Validation Suite | What's in a test, how to run the suite, and how to add a new test. |
| Cross Compiler | The bundled sparc-elf toolchain used to assemble and compile test programs. |
Logging and Monitoring¶
| Page | Description |
|---|---|
| Logging | How instruction-trace logging works, compile-time and runtime, and the log viewer. |
| Examining Core State with GDB | A beginner-facing walkthrough of debugging a running model with gdb. |
| GDB Command Reference | The exhaustive reference for every sparc-* gdb command. |
| Debug Support Internals | How gdb support is actually built, for anyone extending debug/sparc.gdb itself. |
The Model¶
| Page | Description |
|---|---|
| SPARC V8 Architecture | A page-indexed guide into the bundled SPARC V8 manual PDF. |
| Model Configurations | A block-diagram-level summary of each testbench configuration, current and planned. |
| Model Components | Describes each component in detail: SparcCore, Mmu, Memory, Caches, and Devices. |
| Peripheral Devices | Overview, connection diagram, address map, and interrupt levels for the peripherals below. |
| Timer | Register format, one-shot countdown behavior, and state machine. |
| Interrupt Controller | Per-core IRC register format, interrupt sources, priority, and the planned multi-core extension. |
| Serial Device | UART register format, baud-rate calculation, and the Tx/Rx state machines. |
| Model Components Reference | A complete, per-file table of every Sitar module/procedure. |
| Model Configuration Settings | Every structural and timing setting in the model, where to set it, compile time or runtime. |
| Performance Modeling | How to print the model's performance measures with --stats, and the table of what's reported. |
More¶
| Page | Description |
|---|---|
| Development Notes | For contributors: repository layout, extending the core, adding tests. |
| Authors | Who built this project, and credits for the adapted validation suite. |
| License | The MIT License this project is released under. |